Modern AI has moved beyond simple text generation to become a formidable partner in electronic engineering. For PCB designers, leveraging Large Language Models (LLMs) means accelerating the transition from schematic to layout, reducing errors in constraint management, and optimizing for manufacturing with unprecedented speed.
These prompts have been rigorously tested and optimized for use across all major AI models, including ChatGPT, Gemini, Claude, and DeepSeek. While each model possesses unique architectural strengths—such as DeepSeek’s coding logic or Claude’s technical nuance—the following 10 prompts provide a universal foundation for increasing efficiency in PCB design and Altium Designer workflows.
1. Automating Repetitive Tasks with Scripts
Best for: DeepSeek (Excellent for logic generation and code syntax)
Writing scripts for Altium Designer (using DelphiScript or Python) can automate tedious tasks like renaming components or generating output files, but the syntax is often obscure.
Act as a Senior PCB Engineer proficient in Altium Designer scripting. Write a script [insert language, e.g., DelphiScript] that iterates through all components in the current PCB document. The script should identify any component with the designator prefix 'R' (Resistors) and ensure their "Comment" field is set to visible. Add comments to the code explaining each step of the API usage.
The Payoff: Instantly generates functional boilerplate code to automate manual property edits, saving hours of clicking through the Properties panel.
2. High-Speed Stackup & Impedance Planning
Best for: Claude (Superior for handling complex, nuanced technical explanations)
Defining the correct layer stackup is critical for signal integrity. This prompt helps you calculate preliminary impedance requirements before entering them into the Layer Stack Manager.
I am designing a 6-layer PCB for a high-speed digital application involving DDR memory. I need a stackup recommendation that achieves 50-ohm single-ended and 100-ohm differential impedance. Assume standard FR-4 material (Dielectric Constant ~4.2). Provide a proposed layer arrangement (Signal-Ground-Power, etc.) and estimate the required trace widths and separation distances to hit these impedance targets. Explain the reasoning regarding return paths and crosstalk.
The Payoff: Provides a mathematically sound starting point for your stackup, ensuring you approach the simulation phase with a viable physical configuration.
3. Rapid Component Comparison & Selection
Best for: Gemini (Strong at processing live data and large comparative sets)
Selecting the right IC involves balancing cost, availability, and specs. This prompt forces the AI to act as a parametric search engine.
Create a comparison table for 3 different Step-Down (Buck) Regulator ICs suitable for the following specifications: Input Voltage 12V-24V, Output Voltage 3.3V, Output Current 3A, and Surface Mount package. Compare them based on: 1. Efficiency, 2. Switching Frequency, 3. Package Size, 4. External Component Count, and 5. General Availability/Cost tier. Recommend the best option for a space-constrained design.
The Payoff: Condenses hours of datasheet browsing into a clear decision matrix, helping you select components that fit both electrical and mechanical constraints.
4. Formulating Complex Design Rules (DRC)
Best for: ChatGPT (Versatile and clear at structuring rule logic)
Setting up Query Helper syntax in Altium or other tools can be error-prone. This prompt helps translate human intent into precise design rule queries.
I need to create a specific Design Rule Check (DRC) query in Altium Designer. The rule should apply a clearance constraint of 20 mils, but ONLY between nets belonging to the "HighVoltage" class and any polygon pours connected to GND. Write the exact Query Helper syntax required to target this specific interaction and explain how to apply it in the Rules Editor.
The Payoff: Eliminates syntax errors in the Query Helper, ensuring safety-critical clearances are strictly enforced without creating false positives.
5. Decoding & Summarizing Datasheets
Best for: Gemini (Large context window allows for uploading/pasting extensive text)
When integrating a complex MCU or FPGA, missing a pin configuration note can be fatal. Use this to extract critical integration details.
[Paste or Upload Datasheet Section for specific IC]
Analyze the "Power Supply Decoupling" and "Layout Guidelines" sections of this datasheet. Summarize the mandatory requirements for:
1. Capacitor values and placement proximity.
2. Ground plane partition recommendations.
3. Trace width requirements for power pins.
Output this as a checklist I can use during the layout phase.
The Payoff: Extracts the “must-have” layout constraints buried in 100+ page datasheets, converting them into an actionable checklist.
6. Troubleshooting EMI/EMC Failures
Best for: DeepSeek (Strong grasp of physics and engineering logic)
When a board fails emissions testing, you need a physicist, not just a layout artist. This prompt helps diagnose potential sources of radiation.
My PCB failed radiated emissions testing at 125MHz. The design includes a microcontroller running at 25MHz and a switching regulator at 500kHz. Based on these frequencies, analyze potential sources of the noise (e.g., harmonics). Suggest 5 specific layout techniques or component additions (such as ferrites, snubbers, or shielding) to mitigate radiation at this specific harmonic.
The Payoff: Provides a root-cause analysis based on harmonic frequency calculation, offering targeted engineering fixes rather than guesses.
7. IPC-Compliant Footprint Creation
Best for: Claude (High attention to standard adherence and detail)
Creating footprints from scratch is risky. This prompt ensures you follow industry standards.
I need to create a footprint for a QFN-32 package (5x5mm body, 0.5mm pitch). Based on IPC-7351 guidelines, guide me through the dimension calculations for:
1. Pad length and width extensions (Toe, Heel, Side fillets).
2. The thermal pad paste mask segmentation (to avoid solder voiding).
3. The courtyard excess.
Provide the dimensions I should use to ensure a "Nominal" density level.
The Payoff: Reduces the risk of solder bridges or open joints by validating your footprint geometry against IPC density levels before you commit to the library.
8. Optimizing Component Placement Strategy
Best for: ChatGPT (Good for general spatial logic and workflow planning)
Placement is 90% of the battle. This prompt helps strategize the flow of the board before routing begins.
I am designing a 4-layer mixed-signal board containing an Analog Front End (AFE), a digital MCU, and a Wi-Fi module. The board inputs 24V and regulates down to 3.3V. Describe the ideal floorplanning strategy to minimize noise coupling. Specifically, address where to place the power supply section relative to the AFE and how to orient the Wi-Fi antenna connector.
The Payoff: Prevents critical signal integrity issues early by establishing a logical physical flow that separates noisy switching regulators from sensitive analog signals.
9. Automating BOM Consolidation
Best for: Gemini (Excellent at data formatting and cleaning)
BOM management often involves cleaning messy Excel data. Use AI to standardize descriptions and manufacturer part numbers (MPNs).
I have a raw Bill of Materials (BOM) where the "Description" column is inconsistent (e.g., some say "10uF Cap," others "Capacitor 10 microfarad").
[Paste small sample of BOM rows]
Rewrite these descriptions to follow a strict standard format: "[Component Type], [Value], [Voltage/Rating], [Package], [Tolerance]". Ensure the format is identical for all entries.
The Payoff: Turns a messy export into a professional, procurement-ready document, reducing questions from purchasing departments or assembly houses.
10. Design for Manufacturing (DFM) Review
Best for: Claude (Detail-oriented review capability)
Before sending gerbers to the fab house, use this prompt to catch expensive manufacturing issues.
Act as a CAM engineer at a PCB fabrication house. Review the following design parameters for a standard 4-layer board and identify any "high-cost" or "high-risk" features:
- Min Trace/Space: 3 mil / 3 mil
- Min Drill Size: 0.15mm
- Annular Ring: 3 mil
- Surface Finish: ENIG
- Copper Weight: 2oz on inner layers
Explain which of these specs might trigger a price increase or yield issues, and suggest standard alternatives (e.g., changing 3 mil space to 5 mil).
The Payoff: saves money and prevents production delays by identifying “heroic” manufacturing constraints that can be relaxed without impacting performance.
Pro-Tip: Context Injection
To get the most out of these prompts, always “prime” the AI with the specific constraints of your CAD tool and manufacturer capabilities. Before asking for a routing strategy, paste your fabricator’s capabilities summary (e.g., “Min track 5mil, Min drill 8mil”). This prevents the AI from suggesting geometries that are electrically perfect but physically impossible to manufacture cheaply.
Mastering the Future of Layout
The difference between a junior designer and a senior lead often lies in the ability to anticipate problems before they are etched in copper. By integrating these AI prompts into your daily workflow—whether for scripting in Altium, calculating impedance, or double-checking DFM rules—you elevate your role from simple layout execution to strategic engineering oversight. Keep refining your prompt library, and let the AI handle the calculation while you focus on the architecture.